1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly, it relates to a semiconductor memory device which can inhibit an overshoot and an undershoot of an output signal waveform.
2. Description of the Background Art
In general, a semiconductor memory device comprises an output buffer circuit which receives a signal of a memory cell amplified by a sense amplifier and generates an external output signal. The external output signal generated in the output buffer circuit is outputted to the exterior of the semiconductor memory device through an output pad, for driving a load which is connected externally such as an external transmission line or another semiconductor memory device connected to the end of an external transmission line, for example.
FIG. 25 is a block diagram schematically showing the structure of a principal part of a static random access memory (hereinafter referred to as an SRAM) 900, which is an exemplary conventional semiconductor memory device. The conventional SRAM 900 comprises an address buffer circuit 52, a row decoder 53, a column decoder 54, memory blocks #1 to #4, a block selection circuit 55, a write driver group 59, and a sense amplifier group 60.
The address buffer circuit 52 receives signals from external address pins XA1 to XA8, YA1 to YA8 and ZA1 and ZA2, and generates internal row address signals X1 to X8, internal column address signals Y1 to Y8 and block address signals Z1 to Z4 respectively. The row decoder 53 receives the internal row address signals X1 to X8 and decodes the same, for raising the potential of a word line selected from a plurality of word lines WL forming a memory cell array 56 described later. The column decoder 54 receives the internal column address signals Y1 to Y8 and decodes the same, for selecting any of a plurality of pairs of bit lines BL and /BL forming the memory cell array 56 described later. The block selection circuit 55 receives the internal block address signals Z1 to Z4 and decodes the same, for generating block selection signals BS1 to BS4. The block selection signals BS1 to BS4 select a sense amplifier 61 described later which is connected with a data bus DB0 among a plurality of sense amplifiers 61 included in the sense amplifier group 60.
FIG. 26 is a circuit diagram for illustrating the structure of each memory block provided in the conventional SRAM 900. This figure representatively shows a structure in relation to the memory block #1.
The memory block #1 comprises the memory cell array 56. The memory cell array 56 includes a plurality of memory cells MC which are arranged in the form of a matrix in row and column directions, a plurality of word lines WL each connected with a row of memory cells MC, and a plurality of pairs of bit lines BL and /BL each connected with a column of memory cells MC.
FIG. 27 is a circuit diagram schematically showing an exemplary structure of each memory cell MC employed in the conventional SRAM 900. The high-resistance load memory cell MC shown in FIG. 27 includes resistors R1 and R2, N-channel field-effect transistors (hereinafter referred to as NMOS transistors) Q53 and Q54 which are drive transistors, and NMOS transistors Q51 and Q52 which are access transistors.
The resistor R1 and the NMOS transistor Q53 as well as the resistor R2 and the NMOS transistor Q54 are serially connected between internal power supply potentials VCC and ground potentials VSS respectively. The gate of the NMOS transistor Q53 is connected to a node N51 corresponding to a connection point between the resistor R2 and the NMOS transistor Q54, while that of the NMOS transistor Q54 is connected to a node N50 corresponding to a connection point between the resistor R1 and the NMOS transistor Q53.
The NMOS transistor Q51 has a first conducting terminal which is connected with the bit line BL, a second conducting terminal which is connected with the node N50, and a gate which is connected with the word line WL. The NMOS transistor Q52 has a first conducting terminal which is connected with the bit line /BL, a second conducting terminal which is connected with the node N51, and a gate which is connected with the word line WL.
Referring again to FIG. 26, the memory block #1 further comprises a bit line load circuit 57 and data multiplexers 58. The bit line load circuit 57 is adapted to apply a proper voltage bias to the memory cells MC. The data multiplexers 58 are circuits employed for inputting/outputting signals from/to the memory cell array 56. The data multiplexers 58 receive the internal column address signals Y1 and Y2 outputted from the column decoder 54, for connecting a selected pair of bit lines BL and /BL with the sense amplifier 61 described later. A write driver 63 shown in FIG. 26, which is a circuit included in the write driver group 59 shown in FIG. 25, receives a signal on the data bus DB0 and writes the same in the corresponding memory block #1.
The sense amplifier 61 shown in FIG. 26, which is a circuit included in the sense amplifier group 60 shown in FIG. 25, amplifies slight potential changes of the selected pair of bit lines BL and /BL. Each sense amplifier 61 receives a corresponding one of the block selection signals BS1 to BS4 outputted from the block selection circuit 55. A single sense amplifier 61 is selected on the basis of each block selection signal. The selected sense amplifier 61 outputs an internal read signal D on the data bus DB0 described later.
Referring again to FIG. 25, the conventional SRAM 900 further includes the data bus DB0, an input buffer circuit 62, and an output buffer circuit 50. The data bus DB0 is a transmission line connecting the sense amplifier group 60 with the output buffer circuit 50. The input buffer circuit 62 converts external input data received from an input/output terminal DQ to an internal write signal in a write operation. The output buffer circuit 50 receives the internal read signal D transmitted from the data bus DB0 in a read operation, and generates an external output signal. This external output signal is outputted from the input/output terminal DQ to the exterior, for driving an external load.
FIG. 28 is a block diagram schematically showing a structure in relation to the output buffer circuit 50 in the conventional SRAM 900. This figure representatively shows connection between the sense amplifier 61 corresponding to the memory block #1 and the output buffer circuit 50.
An output node of the sense amplifier 61 is connected to the data bus DB0. An end of the data bus DB0 is connected to an input node of the output buffer circuit 50. An output node of the output buffer circuit 50 is connected to an output pad P1. A P-channel field-effect transistor (hereinafter referred to as a PMOS transistor) Q23 has a first conducting terminal which is connected with the internal power supply potential VCC, a second conducting terminal which is connected onto the data bus DB0, and a gate receiving an internal write enable signal /WE.
When the internal write enable signal /WE is at a low level, the PMOS transistor Q23 enters a conducting state, and the potential of the data bus DB0 goes high. When the internal write enable signal /WE is at a high level, on the other hand, the PMOS transistor Q23 enters a non-conducting state. In case of a non-write operation (the internal write enable signal /WE is at a high level), therefore, the internal read signal D outputted from the sense amplifier 61 selected on the basis of the block selection signal BS1 is transmitted to the output buffer circuit 50 through the data bus DB0. In case of a write operation (the internal write enable signal /WE is at a low level), on the other hand, the potential on the data bus DB0 goes high, for preventing the data bus DB0 from entering a floating state.
FIG. 29 is a circuit diagram schematically showing the structure of the output buffer circuit 50 included in the conventional SRAM 900. The output buffer circuit 50 shown in FIG. 29, which is a tri-state output buffer circuit, outputs a signal of a high level, a low level, or a high impedance (non-read state) value. The output buffer 50 receives the internal read signal D outputted from the sense amplifier 61 at its input through the data bus DB0.
Referring to FIG. 29, the output buffer circuit 50 comprises a pre-buffer circuit 70, and an output stage 1 corresponding to an output final stage. The pre-buffer circuit 70 includes a NAND circuit NA1, a NOT circuit NT1, and a NOR circuit NR1. The NAND circuit NA1 receives an output enable signal OE and the internal read signal D. The NOT circuit NT1 receives the output enable signal OE and outputs an internal output enable signal /OE obtained by inverting the same. The NOR circuit NR1 receives the internal output enable signal /OE outputted from the NOT circuit NT1 and the internal read signal D. The output enable signal OE is in an activated state (high level) in a read operation, and in an inactivated state (low level) in a non-read operation.
The output stage 1 comprises a PMOS transistor Q5a and an NMOS transistor Q6a which are complementarily connected between the internal power supply potential VCC and the ground potential VSS. The gates of the PMOS transistor Q5a and the NMOS transistor Q6a receive signals C1 and C2 outputted from the NAND circuit NA1 and the NOR circuit NR1 respectively. A node N0, which is a connection point between first conducting terminals of the PMOS transistor Q5a and the NMOS transistor Q6a, is connected to the output pad P1.
Operations of the conventional output buffer circuit 50 are now described. With reference to FIG. 30A, an operation of the output buffer circuit 50 receiving the internal read signal D of a high level at its input in a read operation (the output enable signal OE is at a high level) is now described.
Referring to FIG. 30B, the NAND circuit NA1 receives the output enable signal OE of a high level and the internal read signal D of a high level, and outputs the signal C1 of a low level. Referring to FIG. 30C, on the other hand, the NOR circuit NR1 receives the internal output enable signal /OE of a low level outputted from the NOT circuit NT1 and the internal read signal D of a high level, and outputs the signal C2 of a low level.
Receiving the signals C1 and C2 of a low level, the PMOS transistor Q5a and the NMOS transistor Q6a enter a conducting state and a non-conducting state respectively. In this case, the node N0 is charged to the level of the internal power supply potential VCC. Referring to FIG. 30D, the output pad P1 consequently outputs an external output signal VOUT of a high level.
With reference to FIG. 31A, an operation of the output buffer circuit 50 receiving the internal read signal D of a low level at its input in a read operation is described.
Referring to FIG. 31B, the NAND circuit NA1 receives the output enable signal OE of a high level and the internal read signal D of a low level, and outputs the signal C1 of a high level. Referring to FIG. 31C, on the other hand, the NOR circuit NR1 receives the internal output enable signal /OE of a low level outputted from the NOT circuit NT1 and the internal read signal D of a low level, and outputs the signal C2 of a high level.
Receiving the signals C1 and C2 of a high level, the PMOS transistor Q5a and the NMOS transistor Q6a enter a non-conducting state and a conducting state respectively. In this case, the node N0 is discharged to the level of the ground potential VSS. Consequently, the output pad P1 outputs the external output signal VOUT of a low level.
In a non-read operation (the output enable signal OE is at a low level), the NAND circuit NA1 receives the output enable signal OE of a low level, and outputs the signal C1 of a high level. On the other hand, the NOR circuit NR1 receives the internal output enable signal /OE of a high level outputted from the NOT circuit NT1, and outputs the signal C2 of a low level.
Receiving the signals C1 and C2 of high and low levels, both the PMOS transistor Q5a and the NMOS transistor Q6a enter non-conducting states. Consequently, the node N0, i.e., the output pad P1 enters a high impedance state.
FIG. 32 is a circuit diagram showing the structure of another conventional output buffer 51, which can be employed in place of the output buffer circuit 50 shown in FIG. 29. The output buffer circuit 51 shown in FIG. 32 comprises a pre-buffer circuit 71 comprising NAND circuits NA2 and NA3 and NOT circuits NT2 to NT4, and an output stage 1.
The output buffer circuit 50 provided in the conventional semiconductor memory device has the following problems:
First, the sense amplifier group 60 transmits signals to the output buffer circuit 50 through the data bus DB0. Therefore, the sense amplifier group 60 must drive a high capacitance toward the output buffer circuit 50. Thus, signal transmission takes much time, leading to a long time for transition of the external output signal VOUT.
Further, MOS transistors forming the pre-buffer circuit 70 drive only the capacitances of the PMOS transistor Q5a and the NMOS transistor Q6a forming the output stage 1. Therefore, the signals C1 and C2 outputted from the pre-buffer circuit 70 have steep waveforms. Thus, there is the possibility that an overshoot and an understood result in the external output signal VOUT outputted from the output stage 1 at an external transmission end portion.
FIGS. 33A, 33B and 33C show changes of the signals C1 and C2, a change of the external output signal VOUT, and states of an overshoot and an undershoot at the external transmission line end portion respectively for illustrating the problem of the conventional semiconductor memory device. Distortion of the signal waveform such as the overshoot or the undershoot serves as a noise source for a peripheral circuit connected externally, to cause loss in an access time or a malfunction on a receiver externally connected, for example. In order to solve this problem, the gate widths W of the MOS transistors forming the output stage 1 corresponding to the output final stage may be reduced for suppressing current drivability. However, this method is limited due to reduction of charge/discharge currents from the output stage 1.
In general, therefore, the gate widths W of the MOS transistors forming the pre-buffer circuit 70 is reduced for retarding rise and fall times of the signal waveforms inputted to the output stage 1. According to this method, it is possible to retard the rise and fall times of the waveform of the external output signal VOUT (through rate control) by retarding the switching rate at the output stage 1.
In this method, however, the waveform of each signal outputted from the sense amplifier group 60 is temporarily dulled by the capacitance of the data bus DB0, then steepened in the pre-buffer circuit 70, and further dulled in the output stage 1 again. This disadvantageously leads to loss of the access time.